BibTeX:

@article{IJIRSTV1I12013,
     title={FPGA Implementation of Median Filter Using an Improved Algorithm for Image Processing},
     author={Eric Ateng},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={1},
     number={12},
     pages={25--30},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV1I12013.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

To solve the contradiction between the noise reducing effect and the time complexity of the standard median filter algorithm, this paper proposed an improved median filter algorithm. This paper focuses on a 3x3 image window filtering in which the sorting network of the filter should be able to produce the desired result within the shortest time possible. That means, the sorting network will be able to exercise parallelism in processing the image pixel and the number of the required hardware maintained minimal. The algorithm derived shows that the sorting network will be able to produce the result within the required time. The improved filter algorithm was implemented using Hardware Description Language Verilog, simulated using Xilinx isim and was loaded on to Xilinx FPGA. The hardware result showed that this proposed algorithm has better output result as compared to standard median algorithm as well as adaptive median algorithm. It has a good application prospect in real-time image processing.

FPGAs, PSNR, Standard Median Filter, Adaptive Median Filter, Processing Element, Salt and Pepper noise