IJIRST (International Journal for Innovative Research in Science & Technology)ISSN (online) : 2349-6010

 International Journal for Innovative Research in Science & Technology

Schematic Design and Process Variation of Low Power High Speed SRAM Cell and DRAM Cell using CMOS Sub-Micron Technology


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International Journal for Innovative Research in Science & Technology
Volume 1 Issue - 12
Year of Publication : 2015
Authors : Viplav A.Soliv

BibTeX:

@article{IJIRSTV1I12164,
     title={Schematic Design and Process Variation of Low Power High Speed SRAM Cell and DRAM Cell using CMOS Sub-Micron Technology},
     author={Viplav A.Soliv},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={1},
     number={12},
     pages={532--539},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV1I12164.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}



Abstract:

SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems. This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) Cell and Dynamic Random Access Memory (DRAM) Cell to perform high speed to develop low power consumption. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 6-transistor SRAM cell built from a simple static latch and tri state inverter and 3-transistor DRAM cell. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines. Results show good performance.


Keywords:

6T SRAM cell, Low power, SRAM, 3T1D DRAM


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