BibTeX:

@article{IJIRSTV1I3010,
     title={Hardware Implementation of Functional Verification Using Signature Analysis},
     author={ Sethulakshmi.R and Greeshma.R},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={1},
     number={3},
     pages={41--43},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV1I3010.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

The main consequences facing in the semiconductor technology is the testing time, and the one of the solution for it is the BIST, which allows the system to check itself. In these paper the functional test is done sing BIST, that is we checking whether the circuit is behaved as intended. BIST implementation techniques are of different types, in all of the techniques the main disadvantage is that as the size of the CUT changes the LFSR and the MISR also need to change, So to overcome that we designing a BIST processor that can test the circuit unto sixteen bits.

BIST, CUT, LFSR, MISR