IJIRST (International Journal for Innovative Research in Science & Technology)ISSN (online) : 2349-6010

 International Journal for Innovative Research in Science & Technology

Aging-Aware Reliable Super Column Multiplier Design with Adaptive Hold Logic for Finite Impulse Response Filter


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International Journal for Innovative Research in Science & Technology
Volume 3 Issue - 8
Year of Publication : 2017
Authors : Shital Tatyaso Atole

BibTeX:

@article{IJIRSTV3I8074,
     title={Aging-Aware Reliable Super Column Multiplier Design with Adaptive Hold Logic for Finite Impulse Response Filter},
     author={Shital Tatyaso Atole},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={3},
     number={8},
     pages={122--127},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV3I8074.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}



Abstract:

In VLSI, scaling methods are very important in reducing the power dissipation. The two major constraints for delay in any VLSI circuits are latency and throughput. In many digital systems we are using digital multipliers. The overall performance of digital systems depends on the throughput of the multiplier. But there are two effects that degrade the transistors throughput and so it degrades the speed of transistors and after long time, system may fail due to timing violations. These two effects are 1) Negative Bias Temperature Instability (NBTI), 2) Positive Bias Temperature Instability (PBTI) effect. Negative Bias Temperature Instability (NBTI) effect means when a pMOS transistor is under negative bias, increasing the threshold voltage (Vth) of the pMOS transistor, and reducing multiplier speed. A same phenomenon, Positive Bias Temperature Instability (PBTI), occurs when an nMOS transistor is under positive bias. Therefore it is important to design reliable high-performance multipliers. The new approach is an aging-aware super column multiplier design with Adaptive Hold Logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to reduce performance degradation that is due to the aging effect.


Keywords:

Adaptive Hold Logic (AHL), Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), Reliable Multiplier, Variable Latency


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