BibTeX:

@article{IJIRSTV2I2053,
     title={Design and Synthesis of 16 Bit Adaptive Digital Filter Architecture},
     author={Nishi Gupta, Rakesh Joon and Ruby Garg},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={2},
     number={2},
     pages={87--93},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV2I2053.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then digital filtering algorithms can be implemented to estimate the signals statistics iteratively. Modern field programmable gate arrays (FPGAs) include the resources needed to design efficient filtering structures. This research aims to combine efficient filter structures with optimized code to create a system-on-chip (SoC) solution for various digital filtering problems. LMS algorithms have been coded in VHDL. The designs are evaluated in terms of filter throughput, hardware resources, and speed performance and to evaluate the mean square error of 16 adaptive digital filters.

LMS, FPGA, VHDL, Soc