BibTeX:

@article{IJIRSTV2I4004,
     title={FPGA Implementation of Error Detection and Correction using Decimal Matrix Code},
     author={Lakshmeepathiputtappa K B and Dr. Sarika Tale},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={2},
     number={4},
     pages={1--9},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV2I4004.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

Currently protection codes are essential to memory cells using to maintain a good reliability, various error detection and error correction methods can be used but to avoid corruption data Error correction code (ECC) are mostly widely used and introduced a delay penalty in accessing the encoding and decoding process can be performed but limitation of ECC are low speed performed in memory .it can be contributed to the utilization of simple code such as single error correction (SEC) and Double error correction (DEC) and detection. Matrix Codes (MC) constructed on hamming codes has been proposed for memory protection. The main dispute is that they are double error correction codes and the error correction capabilities are not enhanced in all cases. Decimal Matrix Code (DMC) structure on matrix and divide symbol is proposed to improve memory reliability with lesser delay. In this thesis, 64-bits and 128-bits Decimal Matrix Code is offered to assure the memory reliability. Here to detect and correct up to 9 and 17 errors respectively. The offered DMC based on decimal algorithm to extended the number of detection and correction capability of error bits stored in memory. More ever structure area of DMC is reduced by reusing its Encoder this is called Encoder Reuse Techniques (ERT). ERT can be used to minimize area without interrupting DMC encoder and decoder. ERT Uses DMC Encoder itself to be a part of decoder. Hence the entire structure area of DMC can be minimized. Using Xilinx Design Suite 14.2 simulation and implementation analysis can be done. Next A Verilog Description has been adopted to embed the low power design.

ECC, DMC, ERT, MC, SEC