BibTeX:

@article{IJIRSTV2I9070,
     title={Implementation of Physical Design of Ternary Inverter with improved characteristic},
     author={Arpit Namdev, M. Abdullah and Shrikant Atkarne},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={2},
     number={9},
     pages={151--156},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV2I9070.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

The ternary logic (also called three-valued or trivalent logic and abbreviated 3VL) is a promising alternative to the conventional binary logic design technique. It is possible for ternary logic to achieve simplicity and energy efficiency in digital design since the logic reduces the complexity of interconnects and chip area, in turn reducing the chip delay. It offers better utilization of transmission channels because of the higher information content carried by each line, also gives more efficient error detection and correction codes and possess potentially higher density of information storage. The proposed paper is aimed to achieve the low power consumption, high stability physical design of ternary inverter. Here we used Microwind EDA tool for designing and simulation of the physical design.

MVL, Ternary arithmetic, CMOS 45 nm Technology, Physical Design