BibTeX:

@article{IJIRSTV5I6004,
     title={Low Power and High Speed Carry Select Adder using Skip Logic},
     author={G. Naveen Balaji, B. Indhumathi, K. Ishwarya, K. Jamuna and T. Prabhu},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={5},
     number={6},
     pages={58--62},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV5I6004.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

This paper clearly focused on Carry Skip Adder (CSA) which gives an advantage of reducing delay, area and power. Usually Ripple carry adder which is used to perform arithmetic operations to perform fast design duration compared with other conventional methods, but lacks with a limitation of generating carry bits. The proposed architecture is designed using Verilog HDL and is then synthesized using Xilinx.

Carry select adder (CSLA), Carry skip adder (CSA), delay, power consumption