IJIRST (International Journal for Innovative Research in Science & Technology)ISSN (online) : 2349-6010

 International Journal for Innovative Research in Science & Technology

Low Power and Area Efficient Carry Save Adder Based on Static 125nm CMOS Technology


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International Journal for Innovative Research in Science & Technology
Volume 5 Issue - 8
Year of Publication : 2019
Authors : G. Naveen Balaji ; D. Hema; B. Indhumathi; M. Ishwarya; G. Hemanth Kumar

BibTeX:

@article{IJIRSTV5I8011,
     title={Low Power and Area Efficient Carry Save Adder Based on Static 125nm CMOS Technology},
     author={G. Naveen Balaji, D. Hema, B. Indhumathi, M. Ishwarya and G. Hemanth Kumar},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={5},
     number={8},
     pages={27--31},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV5I8011.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}



Abstract:

In a digital circuit theory combinational logic is a type of the digital logic implemented by Boolean circuits where the output is dependent of pure present input. A Carry save adder is one of the type of the digital adder that is used in the computer micro architecture to compute the sum of the three or more n-bit binary numbers in binary. It differs from other digital adders in that it outputs two numbers of the same dimension as the inputs one which is a sequence of partial sum bits and another which is a sequence of partial sum bits and another which is a sequence of carry bits. It has few advantages such as it produces all of its outputs in parallel resulting in the same delay as full adder. It has very little propagation delay when implemented. Carry Save adder plus ripple adder is equals to n+1. Two ripple carry adders is equals to 2n. It allows for high clock speeds. Though it is some advantages it also has some disadvantages such as we do not know whether the result is positive a negative. While performing modular multiplication. The behaviour of the efficient Carry Save Adder is designed using tanner eda tools which was useful and the currently existing carry skip adder is designed using xilnx software and lastly the layout for this research is designed with the help of multisim. With help of this research many newly created circuits can designed much smaller.


Keywords:

carry save adder, CMOS, static CMOS, 125nm, tanner, multisim, Xilinx, half adder, Full adder, Ripple carry adder


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