BibTeX:

@article{IJIRSTV5I8012,
     title={Power Efficient Carry Skip Adder Based on Static 125nm CMOS Technology},
     author={G. Naveen Balaji, R. Abinaya, S. Gayathri, S. Atchaya and G. Hemanth Kumar},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={5},
     number={8},
     pages={32--36},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV5I8012.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

In a digital circuit theory, combinational logic is a type of digital logic implemented by Boolean circuits, where the output is pure function of the present input. A carry skip adder which is also known as carry by pass adder is an adder implementation that improves on the delay of a ripple carry adder with little effort compared to other adders, In which, it have the low power consumption, a high degree of regularity and simplicity that the carry ripple chain is connected to n-input AND gate. The resulting bit is used as the select bit a multiplexer that switches either the last carry bit or the carry-in to the carry-out signal. The behaviour of the efficient Carry Skip Adder is designed using tanner eda tools which was useful and the currently existing carry skip adder is designed using xilnx software and lastly the layout for this research is designed with the help of multisim. With help of this research many newly created circuits can designed much smaller.

Carry Skip Adder, CMOS, Static CMOS, 125nm, Tanner, Multisim, Xilinx, Half Adder, Full Adder, Ripple Carry Adder